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CY14B104L, CY14B104N
4 Mbit (512K x 8/256K x 16) nvSRAM
Features

Functional Description
The Cypress CY14B104L/CY14B104N is a fast static RAM, with a nonvolatile element in each memory cell. The memory is organized as 512K bytes of 8 bits each or 256K words of 16 bits each. The embedded nonvolatile elements incorporate QuantumTrap technology, producing the world's most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while independent nonvolatile data resides in the highly reliable QuantumTrap cell. Data transfers from the SRAM to the nonvolatile elements (the STORE operation) takes place automatically at power down. On power up, data is restored to the SRAM (the RECALL operation) from the nonvolatile memory. Both the STORE and RECALL operations are also available under software control.
20 ns, 25 ns, and 45 ns Access Times Internally organized as 512K x 8 (CY14B104L) or 256K x 16 (CY14B104N) Hands off Automatic STORE on power down with only a small Capacitor STORE to QuantumTrap(R) nonvolatile elements initiated by software, device pin, or AutoStore(R) on power down RECALL to SRAM initiated by software or power up Infinite Read, Write, and Recall Cycles 200,000 STORE cycles to QuantumTrap 20 year data retention Single 3V +20% to -10% operation Commercial and Industrial Temperatures 48-ball FBGA and 44/54-pin TSOP II packages Pb-free and RoHS compliance
Logic Block Diagram[1, 2, 3]
Notes 1. Address A0 - A18 for x8 configuration and Address A0 - A17 for x16 configuration. 2. Data DQ0 - DQ7 for x8 configuration and Data DQ0 - DQ15 for x16 configuration. 3. BHE and BLE are applicable for x16 configuration only.
Cypress Semiconductor Corporation Document #: 001-07102 Rev. *L
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised December 19, 2008
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CY14B104L, CY14B104N
Pinouts
Figure 1. Pin Diagram - 48 FBGA
48-FBGA
(x8)
48-FBGA
(x16)
Top View (not to scale)
1 NC NC DQ0 VSS VCC DQ3 2 OE NC NC DQ1 DQ2 NC 3 A0 A3 A5 A17 VCAP A14 A12 A9 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE NC DQ5 DQ6 NC WE A11 6 NC NC DQ4 VCC VSS DQ7 NC NC
[4]
Top View (not to scale)
1 BLE DQ8 2 OE BHE 3 A0 A3 A5 A17 VCAP A14 A12 A9 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE DQ1 DQ3 DQ4 DQ5 WE A11 6 NC DQ0 DQ2 VCC VSS DQ6 DQ7
[5] NC
A B C D E F G H
A B C D E F G H
DQ9 DQ10 VSS DQ11
VCC DQ12 DQ14 DQ13 DQ15 HSB NC
[4]
[5] HSB NC
A18
A8
A8
Figure 2. Pin Diagram - 44 Pin TSOP II
44-TSOP II
(x8)
44-TSOP II
(x16)[6]
NC [5] NC A0 A1 A2 A3 A4 CE DQ0 DQ1 VCC VSS DQ2 DQ3 WE A5 A6 A7 A8 A9 NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
44 - TSOP II
(x8)
Top View (not to scale)
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
HSB NC [4] NC A18 A17 A16 A15 OE DQ7 DQ6 VSS VCC DQ5 DQ4 VCAP A14 A13 A12 A11 A10 NC NC
A0 A1 A2 A3 A4 CE DQ0 DQ1 DQ2 DQ3 VCC VSS DQ4 DQ5 DQ6 DQ7 WE A5 A6 A7 A8 A9
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
44 - TSOP II
(x16)
Top View (not to scale)
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
A17 A16 A15 OE BHE BLE DQ15 DQ14 DQ13 DQ12 VSS VCC DQ11 DQ10 DQ9 DQ8 VCAP A14 A13 A12 A11 A10
Notes 4. Address expansion for 8 Mbit. NC pin not connected to die. 5. Address expansion for 16 Mbit. NC pin not connected to die. 6. HSB pin is not available in 44-TSOP II (x16) package.
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CY14B104L, CY14B104N
Pinouts
(continued) Figure 3. Pin Diagram - 54 Pin TSOP II (x16)
NC [5] NC A0 A1 A2 A3 A4 CE DQ0 DQ1 DQ2 DQ3 VCC VSS DQ4 DQ5 DQ6 DQ7 WE A5 A6 A7 A8 A9 NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 HSB NC [4] A17 A16 A15 OE BHE BLE DQ15 DQ14 DQ13 DQ12 VSS VCC DQ11 DQ10 DQ9 DQ8 VCAP A14 A13 A12 A11 A10 NC NC NC
54 - TSOP II
(x16)
Top View (not to scale)
Pin Definitions
Pin Name A0 - A18 A0 - A17 DQ0 - DQ7 DQ0 - DQ15 WE CE OE BHE BLE VSS VCC HSB
[6]
IO Type Input
Description Address Inputs Used to Select one of the 524,288 bytes of the nvSRAM for x8 Configuration. Address Inputs Used to Select one of the 262,144 words of the nvSRAM for x16 Configuration.
Input/Output Bidirectional Data IO Lines for x8 Configuration. Used as input or output lines depending on operation. Bidirectional Data IO Lines for x16 Configuration. Used as input or output lines depending on operation. Input Input Input Input Input Ground Write Enable Input, Active LOW. When selected LOW, data on the IO pins is written to the specific address location. Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip. Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles. IO pins are tri-stated on deasserting OE HIGH. Byte High Enable, Active LOW. Controls DQ15 - DQ8. Byte Low Enable, Active LOW. Controls DQ7 - DQ0. Ground for the Device. Must be connected to the ground of the system.
Power Supply Power Supply Inputs to the Device. Input/Output Hardware Store Busy (HSB). When LOW this output indicates that a hardware store is in progress. When pulled LOW external to the chip it initiates a nonvolatile STORE operation. A weak internal pull up resistor keeps this pin HIGH if not connected (connection optional). After each store operation HSB will be driven HIGH for short time with standard output high current. Power Supply AutoStore Capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to nonvolatile elements. No Connect No Connect. This pin is not connected to the die. Page 3 of 25
VCAP NC
Document #: 001-07102 Rev. *L
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CY14B104L, CY14B104N
Device Operation
The CY14B104L/CY14B104N nvSRAM is made up of two functional components paired in the same physical cell. They are an SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is transferred to the nonvolatile cell (the STORE operation), or from the nonvolatile cell to the SRAM (the RECALL operation). Using this unique architecture, all cells are stored and recalled in parallel. During the STORE and RECALL operations, SRAM read and write operations are inhibited. The CY14B104L/CY14B104N supports infinite reads and writes similar to a typical SRAM. In addition, it provides infinite RECALL operations from the nonvolatile cells and up to 200K STORE operations. See the "Truth Table For SRAM Operations" on page 15 for a complete description of read and write modes.
Figure 4 shows the proper connection of the storage capacitor (VCAP) for automatic store operation. Refer to DC Electrical Characteristics on page 7 for the size of VCAP. The voltage on the VCAP pin is driven to VCC by a regulator on the chip. A pull up should be placed on WE to hold it inactive during power up. This pull up is only effective if the WE signal is tri-state during power up. Many MPU's will tri-state their controls on power up. This should be verified when using the pull up. When the nvSRAM comes out of power-on-recall, the MPU must be active or the WE held inactive until the MPU comes out of reset. To reduce unnecessary nonvolatile stores, AutoStore and hardware store operations are ignored unless at least one write operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether a write operation has taken place. The HSB signal is monitored by the system to detect if an AutoStore cycle is in progress. Figure 4. AutoStore Mode
Vcc
SRAM Read
The CY14B104L/CY14B104N performs a read cycle when CE and OE are LOW and WE and HSB are HIGH. The address specified on pins A0-18 or A0-17 determines which of the 524,288 data bytes or 262,144 words of 16 bits each are accessed. Byte enables (BHE, BLE) determine which bytes are enabled to the output, in the case of 16-bit words. When the read is initiated by an address transition, the outputs are valid after a delay of tAA (read cycle 1). If the read is initiated by CE or OE, the outputs are valid at tACE or at tDOE, whichever is later (read cycle 2). The data output repeatedly responds to address changes within the tAA access time without the need for transitions on any control input pins. This remains valid until another address change or until CE or OE is brought HIGH, or WE or HSB is brought LOW.
0.1uF 10kOhm Vcc
WE
VCAP
VSS
VCAP
SRAM Write
A write cycle is performed when CE and WE are LOW and HSB is HIGH. The address inputs must be stable before entering the write cycle and must remain stable until CE or WE goes HIGH at the end of the cycle. The data on the common IO pins DQ0-15 are written into the memory if the data is valid tSD before the end of a WE controlled write or before the end of an CE controlled write. The Byte Enable inputs (BHE, BLE) determine which bytes are written, in the case of 16bit words. It is recommended that OE be kept HIGH during the entire write cycle to avoid data bus contention on common IO lines. If OE is left LOW, internal circuitry turns off the output buffers tHZWE after WE goes LOW.
Hardware STORE Operation
The CY14B104L/CY14B104N provides the HSB[6] pin to control and acknowledge the STORE operations. Use the HSB pin to request a hardware STORE cycle. When the HSB pin is driven LOW, the CY14B104L/CY14B104N conditionally initiates a STORE operation after tDELAY. An actual STORE cycle only begins if a write to the SRAM has taken place since the last STORE or RECALL cycle. The HSB pin also acts as an open drain driver that is internally driven LOW to indicate a busy condition when the STORE (initiated by any means) is in progress. When HSB is driven LOW by any means, SRAM read and write operations that are in progress are given time to complete before the STORE operation is initiated. After HSB goes LOW, the CY14B104L/CY14B104N continues SRAM operations for tDELAY. During any STORE operation, regardless of how it is initiated, the CY14B104L/CY14B104N continues to drive the HSB pin LOW, releasing it only when the STORE is complete. Upon completion of the STORE operation, the CY14B104L/CY14B104N remains disabled until the HSB pin returns HIGH. Leave the HSB unconnected if it is not used.
AutoStore Operation
The CY14B104L/CY14B104N stores data to the nvSRAM using one of the following three storage operations: Hardware Store activated by HSB; Software Store activated by an address sequence; AutoStore on device power down. The AutoStore operation is a unique feature of QuantumTrap technology and is enabled by default on the CY14B104L/CY14B104N. During a normal operation, the device draws current from VCC to charge a capacitor connected to the VCAP pin. This stored charge is used by the chip to perform a single STORE operation. If the voltage on the VCC pin drops below VSWITCH, the part automatically disconnects the VCAP pin from VCC. A STORE operation is initiated with power provided by the VCAP capacitor.
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CY14B104L, CY14B104N
Hardware RECALL (Power Up)
During power up or after any low power condition (VCC< VSWITCH), an internal RECALL request is latched. When VCC again exceeds the sense voltage of VSWITCH, a RECALL cycle is automatically initiated and takes tHRECALL to complete. During this time, HSB is driven LOW by the HSB driver.
Software STORE
Transfer data from the SRAM to the nonvolatile memory with a software address sequence. The CY14B104L/CY14B104N software STORE cycle is initiated by executing sequential CE controlled read cycles from six specific address locations in exact order. During the STORE cycle an erase of the previous nonvolatile data is performed, followed by a program of the nonvolatile elements. After a STORE cycle is initiated, further input and output are disabled until the cycle is completed. Because a sequence of READs from specific addresses is used for STORE initiation, it is important that no other read or write accesses intervene in the sequence. Further, no read or write operations must be done after the sixth address read for a duration of soft-sequence processing time (tSS). If these conditions are not met, the sequence is aborted and no STORE or RECALL takes place. To initiate the software STORE cycle, the following addresses and read sequence must be performed. 1. Read Address 0x4E38 Valid READ 2. Read Address 0xB1C7 Valid READ 3. Read Address 0x83E0 Valid READ 4. Read Address 0x7C1F Valid READ 5. Read Address 0x703F Valid READ 6. Read Address 0x8FC0 Initiate STORE Cycle Table 1. Mode Selection CE H L L L WE X H L H OE, BHE, BLE[3] X L X L
The software sequence may be clocked with CE controlled reads or OE controlled reads. After the sixth address in the sequence is entered, the STORE cycle commences and the chip is disabled. HSB will be driven LOW. It is important to use read cycles and not write cycles in the sequence, although it is not necessary that OE be LOW for a valid sequence. After the tSTORE cycle time is fulfilled, the SRAM is activated again for the read and write operation.
Software RECALL
Transfer the data from the nonvolatile memory to the SRAM with a software address sequence. A software RECALL cycle is initiated with a sequence of read operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of CE controlled read operations must be performed. 1. Read Address 0x4E38 Valid READ 2. Read Address 0xB1C7 Valid READ 3. Read Address 0x83E0 Valid READ 4. Read Address 0x7C1F Valid READ 5. Read Address 0x703F Valid READ 6. Read Address 0x4C63 Initiate RECALL Cycle Internally, RECALL is a two step procedure. First, the SRAM data is cleared; then, the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time, the SRAM is again ready for read and write operations. The RECALL operation does not alter the data in the nonvolatile elements.
A15 - A0[7] X X X 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x8B45
Mode Not Selected Read SRAM Write SRAM Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM AutoStore Disable
IO Output High Z Output Data Input Data Output Data Output Data Output Data Output Data Output Data Output Data
Power Standby Active Active Active[8, 9]
Notes 7. While there are 19 address lines on the CY14B104L (18 address lines on the CY14B104N), only the 13 address lines (A14 - A2) are used to control software modes. The rest of the address lines are don't care. 8. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle. 9. IO state depends on the state of OE, BHE, and BLE. The IO table shown assumes OE, BHE, and BLE LOW.
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CY14B104L, CY14B104N
Table 1. Mode Selection (continued) CE L WE H OE, BHE, BLE[3] L A15 - A0[7] 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x4B46 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x8FC0 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x4C63 Mode Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM AutoStore Enable Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile Store Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile Recall IO Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output High Z Output Data Output Data Output Data Output Data Output Data Output High Z Power Active[8, 9]
L
H
L
Active ICC2[8, 9]
L
H
L
Active[8, 9]
Preventing AutoStore
The AutoStore function is disabled by initiating an AutoStore disable sequence. A sequence of read operations is performed in a manner similar to the software STORE initiation. To initiate the AutoStore disable sequence, the following sequence of CE controlled read operations must be performed: 1. Read address 0x4E38 Valid READ 2. Read address 0xB1C7 Valid READ 3. Read address 0x83E0 Valid READ 4. Read address 0x7C1F Valid READ 5. Read address 0x703F Valid READ 6. Read address 0x8B45 AutoStore Disable The AutoStore is re-enabled by initiating an AutoStore enable sequence. A sequence of read operations is performed in a manner similar to the software RECALL initiation. To initiate the AutoStore enable sequence, the following sequence of CE controlled read operations must be performed: 1. Read address 0x4E38 Valid READ 2. Read address 0xB1C7 Valid READ 3. Read address 0x83E0 Valid READ 4. Read address 0x7C1F Valid READ 5. Read address 0x703F Valid READ 6. Read address 0x4B46 AutoStore Enable
If the AutoStore function is disabled or re-enabled, a manual STORE operation (hardware or software) must be issued to save the AutoStore state through subsequent power down cycles. The part comes from the factory with AutoStore enabled.
Data Protection
The CY14B104L/CY14B104N protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and write operations. The low voltage condition is detected when VCC < VSWITCH. If the CY14B104L/CY14B104N is in a write mode (both CE and WE are LOW) at power up, after a RECALL or STORE, the write is inhibited until the SRAM is enabled after tLZHSB (HSB to output active). This protects against inadvertent writes during power up or brown out conditions.
Noise Considerations
Refer to CY application note AN1064.
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CY14B104L, CY14B104N
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................. -65C to +150C Maximum Accumulated Storage Time At 150C Ambient Temperature ........................ 1000h At 85C Ambient Temperature ...................... 20 Years Ambient Temperature with Power Applied ............................................ -55C to +150C Supply Voltage on VCC Relative to GND ..........-0.5V to 4.1V Voltage Applied to Outputs in High-Z State....................................... -0.5V to VCC + 0.5V Input Voltage.......................................... -0.5V to VCC + 0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential .................. -2.0V to VCC + 2.0V Package Power Dissipation Capability (TA = 25C) ................................................... 1.0W Surface Mount Pb Soldering Temperature (3 Seconds) .......................................... +260C DC Output Current (1 output at a time, 1s duration).... 15 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch Up Current ................................................... > 200 mA
Operating Range
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 2.7V to 3.6V 2.7V to 3.6V
DC Electrical Characteristics
Over the Operating Range (VCC = 2.7V to 3.6V) Parameter Description ICC1 Average VCC Current Test Conditions Min Max 65 65 50 70 70 52 10 35 Unit mA mA mA mA mA mA mA mA
tRC = 20 ns Commercial tRC = 25 ns tRC = 45 ns Values obtained without output loads (IOUT = 0 mA) Industrial
ICC2 ICC3[10]
Average VCC Current during STORE
All Inputs Don't Care, VCC = Max Average current for duration tSTORE
Average VCC Current at All inputs cycling at CMOS levels. tRC= 200 ns, 3V, 25C Values obtained without output loads (IOUT = 0 mA). typical Average VCAP Current All Inputs Don't Care, VCC = Max during AutoStore Cycle Average current for duration tSTORE VCC Standby Current CE > (VCC - 0.2V). All others VIN < 0.2V or > (VCC - 0.2V). Standby current level after nonvolatile cycle is complete. Inputs are static. f = 0 MHz. -1 -100 -1 2.0 VSS - 0.5 IOUT = -2 mA IOUT = 4 mA Between VCAP pin and VSS, 5V Rated 61 2.4
ICC4 ISB IIX[11]
5 5
mA mA
Input Leakage Current VCC = Max, VSS < VIN < VCC (except HSB) Input Leakage Current VCC = Max, VSS < VIN < VCC (for HSB)
+1 +1 +1 VCC + 0.5 0.8 0.4 180
A A A V V V V F
IOZ VIH VIL VOH VOL VCAP[12]
Off-State Output Leakage Current Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage Storage Capacitor
VCC = Max, VSS < VOUT < VCC, CE or OE > VIH or BHE/BLE > VIH or WE < VIL
Notes 10. Typical conditions for the active current shown on the DC Electrical characteristics are average values at 25C (room temperature), and VCC = 3V. Not 100% tested. 11. The HSB pin has IOUT = -2 A for VOH of 2.4V when both active HIGH and LOW drivers are disabled. When they are enabled standard VOH and VOL are valid. This parameter is characterized but not tested. 12. VCAP (Storage capacitor) nominal value is 68 F.
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CY14B104L, CY14B104N
Data Retention and Endurance
Parameter DATAR NVC Data Retention Nonvolatile STORE Operations Description Min 20 200 Unit Years K
Capacitance
In the following table, the capacitance parameters are listed.[13] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 0 to 3.0V Max 7 7 Unit pF pF
Thermal Resistance
In the following table, the thermal resistance parameters are listed. [13] Parameter Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51. 48-FBGA 44-TSOP II 54-TSOP II 28.82 7.84 31.11 5.56 30.73 6.08 Unit C/W C/W
JA JC
Figure 5. AC Test Loads
577 3.0V OUTPUT 30 pF R2 789 R1
577 3.0V OUTPUT 5 pF R1
for tri-state specs
R2 789
AC Test Conditions
Input Pulse Levels.................................................... 0V to 3V Input Rise and Fall Times (10% - 90%)........................ <3 ns Input and Output Timing Reference Levels.................... 1.5V
Note 13. These parameters are guaranteed but not tested.
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CY14B104L, CY14B104N
AC Switching Characteristics
Parameters Cypress Parameters tACE tRC[14] tAA[15] tDOE tOHA[15] tLZCE[16] tHZCE[16] tLZOE[16] tHZOE[16] tPU[13] tPD[13] tDBE tLZBE tHZBE tWC tPWE tSCE tSD tHD tAW tSA tHA tHZWE[16,17] tLZWE[16] tBW Alt Parameters tACS tRC tAA tOE tOH tLZ tHZ tOLZ tOHZ tPA tPS tWC tWP tCW tDW tDH tAW tAS tWR tWZ tOW Description 20 ns Min Max 25 ns Min Max 45 ns Min Max Unit
SRAM Read Cycle Chip Enable Access Time Read Cycle Time Address Access Time Output Enable to Data Valid Output Hold After Address Change Chip Enable to Output Active Chip Disable to Output Inactive Output Enable to Output Active Output Disable to Output Inactive Chip Enable to Power Active Chip Disable to Power Standby Byte Enable to Data Valid Byte Enable to Output Active Byte Disable to Output Inactive Write Cycle Time Write Pulse Width Chip Enable To End of Write Data Setup to End of Write Data Hold After End of Write Address Setup to End of Write Address Setup to Start of Write Address Hold After End of Write Write Enable to Output Disable Output Active after End of Write Byte Enable to End of Write 3 15 20 15 15 8 0 15 0 0 8 3 20 0 8 25 20 20 10 0 20 0 0 10 3 30 0 20 10 0 10 45 30 30 15 0 30 0 0 15 0 8 0 25 12 0 15 3 3 8 0 10 0 45 20 20 20 10 3 3 10 0 15 20 25 25 12 3 3 15 25 45 45 20 45 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
SRAM Write Cycle
Switching Waveforms
Figure 6. SRAM Read Cycle #1: Address Controlled[14, 15, 18]
Notes 14. WE must be HIGH during SRAM read cycles. 15. Device is continuously selected with CE, OE and BHE / BLE LOW. 16. Measured 200 mV from steady state output voltage. 17. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state. 18. HSB must remain HIGH during READ and WRITE cycles.
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CY14B104L, CY14B104N
Figure 7. SRAM Read Cycle #2: CE and OE Controlled[3, 14, 18]
Figure 8. SRAM Write Cycle #1: WE Controlled[3, 17, 18, 19]
Notes 19. CE or WE must be >VIH during address transitions.
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CY14B104L, CY14B104N
Figure 9. SRAM Write Cycle #2: CE Controlled[3, 17, 18, 19]
tWC Address tSA CE tBW BHE, BLE tPWE WE tSD Data Input Data Output Input Data Valid High Impedance tHD Address Valid tSCE tHA
Figure 10. SRAM Write Cycle #3: BHE and BLE Controlled[3, 17, 18, 19]
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CY14B104L, CY14B104N
AutoStore/Power Up RECALL
Parameters tHRECALL [20] tSTORE [21] tDELAY [22] VSWITCH tVCCRISE VHDIS[13] tHHHD tPURHH tLZHSB Description Power Up RECALL Duration STORE Cycle Duration Time Allowed to Complete SRAM Cycle Low Voltage Trigger Level VCC Rise Time HSB Output Driver Disable Voltage HSB High Active Time HSB Hold Time after Power-Up Recall Start HSB To Output Active Time CY14B104L/CY14B104N Min Max 20 8 1 70 2.65 150 1.9 500 70 5 Unit ms ms s V s V ns s s
Switching Waveforms
Figure 11. AutoStore or Power Up RECALL[23]
Notes 20. tHRECALL starts from the time VCC rises above VSWITCH. 21. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware Store takes place. 22. On a Hardware STORE, Software STORE/RECALL, AutoStore Enable/Disable and AutoStore initiation, SRAM operation continues to be enabled for time tDELAY. 23. Read and Write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH. 24. HSB pin is driven HIGH to VCC only by internal 100 k resistor, HSB driver is disabled.
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CY14B104L, CY14B104N
Software Controlled STORE/RECALL Cycle
In the following table, the software controlled STORE/RECALL cycle parameters are listed.[25, 26] Parameters tRC tSA tCW tHA tRECALL tSS [27, 28] Description STORE/RECALL Initiation Cycle Time Address Setup Time Clock Pulse Width Address Hold Time RECALL Duration Soft Sequence Processing Time 20 ns Min Max 20 0 15 0 200 100 25 ns Min Max 25 0 20 0 200 100 45 ns Min Max 45 0 30 0 200 100 Unit ns ns ns ns s s
Switching Waveforms
Figure 12. CE and OE Controlled Software STORE/RECALL Cycle[26]
Figure 13. Autostore Enable / Disable Cycle
Notes 25. The software sequence is clocked with CE controlled or OE controlled reads. 26. The six consecutive addresses must be read in the order listed in Table 1 on page 5. WE must be HIGH during all six consecutive cycles. After the sixth address read cycle, no further read or write operation must be performed for tSS duration. If these conditions are not met, the software sequence is aborted.
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Hardware STORE Cycle
Parameters tPHSB tHLBL Description Hardware STORE Pulse Width Hardware STORE LOW to STORE Busy CY14B104L/CY14B104N Min 15 500 Max Unit ns ns
Switching Waveforms
Figure 14. Hardware STORE Cycle[21]
Figure 15. Soft Sequence Processing[27, 28]
Notes 27. This is the amount of time it takes to take action on a soft sequence command. VCC power must remain HIGH to effectively register command. 28. Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time. See the specific command.
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Truth Table For SRAM Operations
HSB should remain HIGH for SRAM Operations.
For x8 Configuration
CE H L L L WE X H H L OE X L H X High Z Data Out (DQ0-DQ7); High Z Data in (DQ0-DQ7); Inputs/Outputs[2] Read Output Disabled Write Mode Deselect/Power down Standby Active Active Active Power
For x16 Configuration
CE H L L L L L L L L L L WE X X H H H H H H L L L OE X X L L L H H H X X X BHE X H L H L L H L L H L BLE X H L L H L L H L L H Inputs/Outputs[2] High-Z High-Z Data Out (DQ0-DQ15) Data Out (DQ0-DQ7); DQ8-DQ15 in High-Z Data Out (DQ8-DQ15); DQ0-DQ7 in High-Z High-Z High-Z High-Z Data In (DQ0-DQ15) Data In (DQ0-DQ7); DQ8-DQ15 in High-Z Data In (DQ8-DQ15); DQ0-DQ7 in High-Z Mode Deselect/Power down Output Disabled Read Read Read Output Disabled Output Disabled Output Disabled Write Write Write Active Active Active Active Active Active Active Active Active Active Power Standby
Document #: 001-07102 Rev. *L
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CY14B104L, CY14B104N
Ordering Information
Speed (ns) 20 Ordering Code CY14B104L-ZS20XCT CY14B104L-ZS20XIT CY14B104L-ZS20XI CY14B104L-BA20XCT CY14B104L-BA20XIT CY14B104L-BA20XI CY14B104L-ZSP20XCT CY14B104L-ZSP20XIT CY14B104L-ZSP20XI CY14B104N-ZS20XCT CY14B104N-ZS20XIT CY14B104N-ZS20XI CY14B104N-BA20XCT CY14B104N-BA20XIT CY14B104N-BA20XI CY14B104N-ZSP20XCT CY14B104N-ZSP20XIT CY14B104N-ZSP20XI 25 CY14B104L-ZS25XCT CY14B104L-ZS25XIT CY14B104L-ZS25XI CY14B104L-BA25XIT CY14B104L-BA25XI CY14B104N-BA25XCT CY14B104L-ZSP25XCT CY14B104L-ZSP25XIT CY14B104L-ZSP25XI CY14B104N-ZS25XCT CY14B104N-ZS25XIT CY14B104N-ZS25XI CY14B104N-BA25XCT CY14B104N-BA25XIT CY14B104N-BA25XI CY14B104N-ZSP25XCT CY14B104N-ZSP25XIT CY14B104N-ZSP25XI Package Diagram 51-85087 51-85087 51-85087 51-85128 51-85128 51-85128 51-85160 51-85160 51-85160 51-85087 51-85087 51-85087 51-85128 51-85128 51-85128 51-85160 51-85160 51-85160 51-85087 51-85087 51-85087 51-85128 51-85128 51-85128 51-85160 51-85160 51-85160 51-85087 51-85087 51-85087 51-85128 51-85128 51-85128 51-85160 51-85160 51-85160 Package Type 44-pin TSOP II 44-pin TSOP II 44-pin TSOP II 48-ball FBGA 48-ball FBGA 48-ball FBGA 54-pin TSOP II 54-pin TSOP II 54-pin TSOP II 44-pin TSOP II 44-pin TSOP II 44-pin TSOP II 48-ball FBGA 48-ball FBGA 48-ball FBGA 54-pin TSOP II 54-pin TSOP II 54-pin TSOP II 44-pin TSOP II 44-pin TSOP II 44-pin TSOP II 48-ball FBGA 48-ball FBGA 48-ball FBGA 54-pin TSOP II 54-pin TSOP II 54-pin TSOP II 44-pin TSOP II 44-pin TSOP II 44-pin TSOP II 48-ball FBGA 48-ball FBGA 48-ball FBGA 54-pin TSOP II 54-pin TSOP II 54-pin TSOP II Commercial Industrial Commercial Industrial Commercial Industrial Commercial Commercial Industrial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Operating Range Commercial Industrial
Document #: 001-07102 Rev. *L
Page 16 of 25
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CY14B104L, CY14B104N
Ordering Information (continued)
Speed (ns) 45 Ordering Code CY14B104L-ZS45XCT CY14B104L-ZS45XIT CY14B104L-ZS45XI CY14B104L-BA45XCT CY14B104L-BA45XIT CY14B104L-BA45XI CY14B104L-ZSP45XCT CY14B104L-ZSP45XIT CY14B104L-ZSP45XI CY14B104N-ZS45XCT CY14B104N-ZS45XIT CY14B104N-ZS45XI CY14B104N-BA45XCT CY14B104N-BA45XIT CY14B104N-BA45XI CY14B104N-ZSP45XCT CY14B104N-ZSP45XIT CY14B104N-ZSP45XI Package Diagram 51-85087 51-85087 51-85087 51-85128 51-85128 51-85128 51-85160 51-85160 51-85160 51-85087 51-85087 51-85087 51-85128 51-85128 51-85128 51-85160 51-85160 51-85160 Package Type 44-pin TSOP II 44-pin TSOP II 44-pin TSOP II 48-ball FBGA 48-ball FBGA 48-ball FBGA 54-pin TSOP II 54-pin TSOP II 54-pin TSOP II 44-pin TSOP II 44-pin TSOP II 44-pin TSOP II 48-ball FBGA 48-ball FBGA 48-ball FBGA 54-pin TSOP II 54-pin TSOP II 54-pin TSOP II Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Operating Range Commercial Industrial
All parts are Pb-free. The above table contains Preliminary information. Please contact your local Cypress sales representative for availability of these parts.
Document #: 001-07102 Rev. *L
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CY14B104L, CY14B104N
Part Numbering Nomenclature
CY 14 B 104 L - ZS P 20 X C T Option: T - Tape & Reel Blank - Std. Pb-Free
P - 54 Pin Blank - 44 Pin
Temperature: C - Commercial (0 to 70C) I - Industrial (-40 to 85C)
Package: BA - 48 FBGA ZS - TSOP II
Speed: 20 - 20 ns 25 - 25 ns 45 - 45 ns
Data Bus: L - x8 N - x16 Density: 104 - 4 Mb
Voltage: B - 3.0V
NVSRAM 14 - Auto Store + Software Store + Hardware Store
Cypress
Document #: 001-07102 Rev. *L
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CY14B104L, CY14B104N
Package Diagrams
Figure 16. 44-Pin TSOP II (51-85087)
DIMENSION IN MM (INCH) MAX MIN.
22 1
PIN 1 I.D.
11.938 (0.470) 11.735 (0.462)
10.262 (0.404) 10.058 (0.396)
OR E KXA SG
23
44
EJECTOR PIN
TOP VIEW
BOTTOM VIEW
0.800 BSC (0.0315)
0.400(0.016) 0.300 (0.012)
BASE PLANE 0-5 0.10 (.004)
10.262 (0.404) 10.058 (0.396) 0.210 (0.0083) 0.120 (0.0047)
18.517 (0.729) 18.313 (0.721) 0.150 (0.0059) 0.050 (0.0020) 1.194 (0.047) 0.991 (0.039) SEATING PLANE
0.597 (0.0235) 0.406 (0.0160)
51-85087-*A
Document #: 001-07102 Rev. *L
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CY14B104L, CY14B104N
Package Diagrams
(continued) Figure 17. 48-Ball FBGA - 6 mm x 10 mm x 1.2 mm (51-85128)
TOP VIEW
BOTTOM VIEW A1 CORNER O0.05 M C O0.25 M C A B
A1 CORNER O0.300.05(48X) 1 2 3 4 5 6 6 5 4 3 2 1
A B C 10.000.10 10.000.10 0.75 5.25 D E F G H
A B C D E 2.625 F G H
A B 6.000.10
A
1.875 0.75 3.75
0.530.05
0.25 C
B 0.210.05 0.15 C 0.15(4X)
6.000.10
SEATING PLANE 0.36 C 1.20 MAX
51-85128-*D
Document #: 001-07102 Rev. *L
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CY14B104L, CY14B104N
Package Diagrams
(continued) Figure 18. 54-Pin TSOP II (51-85160)
51-85160-**
Document #: 001-07102 Rev. *L
Page 21 of 25
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CY14B104L, CY14B104N
Document History Page
Document Title: CY14B104L/CY14B104N 4 Mbit (512K x 8/256K x 16) nvSRAM Document Number: 001-07102 Rev. ** *A ECN No. 431039 489096 Submission Date See ECN See ECN Orig. of Change TUP TUP New Data Sheet Removed 48 SSOP Package Added 48 FBGA and 54 TSOPII Packages Updated Part Numbering Nomenclature and Ordering Information Added Soft Sequence Processing Time Waveform Removed 35 ns speed bin Added 55 ns speed bin. Updated AC table for the same Changed "Unlimited" read/write to "infinite" read/write Features section: Changed typical ICC at 200-ns cycle time to 8 mA Changed STORE cycles from 500K to 200K cycles Shaded Commercial grade in operating range table Modified Icc/Is specs 48 FBGA package nomenclature changed from BW to BV Modified part nomenclature table. Changes reflected in ordering information table Removed 55ns speed bin Changed pinout for 44TSOPII and 54TSOPII packages Changed ISB to 1mA Changed ICC4 to 3mA Changed VCAP min to 35F Changed VIH max to Vcc + 0.5V Changed tSTORE to 15ms Changed tPWE to 10ns Changed tSCE to 15ns Changed tSD to 5ns Changed tAW to 10ns Removed tHLBL Added Timing Parameters for BHE and BLE - tDBE, tLZBE, tHZBE, tBW Removed min specification for Vswitch Changed tGLAX to 1ns Added tDELAY max of 70us Changed tSS specification from 70us min to 70us max Changed the data sheet from Advance information to Preliminary 48 FBGA package code changed from BV to BA Removed 48 FBGA package in X8 configuration in ordering information. Changed tDBE to 10ns in 15ns part Changed tHZBE in 15ns part to 7ns and in 25ns part to10ns Changed tBW in 15ns part to 15ns and in 25ns part to 20ns Changed tGLAX to tGHAX Changed the value of ICC3 to 25mA Changed the value of tAW in 15ns part to15ns Changed A18 and A19 Pins in FBGA Pin Configuration to NC Included all the information for 45 ns part in this data sheet Description of Change
*B
499597
See ECN
PCI
*C
517793
See ECN
TUP
*D
774001
See ECN
UHA
*E
914220
See ECN
UHA
Document #: 001-07102 Rev. *L
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CY14B104L, CY14B104N
Document Title: CY14B104L/CY14B104N 4 Mbit (512K x 8/256K x 16) nvSRAM Document Number: 001-07102 Rev. *F ECN No. 1889928 Submission Date See ECN Orig. of Change vsutmp8/AESA Description of Change Added Footnotes 1, 2 and 3. Updated logic block diagram Added 48-FBGA (X8) Pin Diagram Changed 8Mb Address expansion Pin from Pin 43 to Pin 42 for 44-TSOP II (x8). Updated pin definitions table. Corrected typo in VIL min spec Changed the value of ICC3 from 25mA to 13mA Changed ISB value from 1mA to 2mA Rearranging of Footnotes. Updated ordering information table Added BHE and BLE Information in Pin Definitions Table Updated Figure 4 (Autostore mode) Updated footnote 6 Changed ICC2 & ICC4 from 3 mA to 6 mA Changed ICC3 from 13 mA to 15 mA Changed Vcap from 35uF min and 57uF max value to 54uF min and 82uF max value Changed ISB from 2 mA to 3 mA Added input leakage current (IIX) for HSB in DC Electrical Characteristics table Corrected typo in tDBE value from 22 ns to 20 ns for 45 ns part Corrected typo in tHZBE value from 22 ns to 15 ns for 45 ns part Corrected typo in tAW value from 15 ns to 10ns for 15 ns part Changed tRECALL from 100 to 200 us Added footnotes 9 and 25; Reframed footnote 14 and 21 Added footnote 14 to figure 7 (SRAM WRITE Cycle #1) Removed 8 mA typical ICC at 200 ns cycle time in Feature section Referenced footnote 8 to ICC3 in DC Characteristics table Changed ICC3 from 15 mA to 35 mA Changed Vcap minimum value from 54 uF to 61 uF Changed tAVAV to tRC Figure 11:Changed tSA to tAS and tSCE to tCW Added 20 ns access speed in "Features" Added ICC1 for tRC=20 ns for both industrial and Commercial temperature Grade updated Thermal resistance table values for 48-FBGA, 44-TSOP II and 54-TSOP II Packages Added AC Switching Characteristics specs for 20 ns access speed Added software controlled STORE/RECALL cycle specs for 20 ns access speed Updated ordering information and part numbering nomenclature
*G
2267286
See ECN
GVCH/PYRS
*H
2483627
See ECN
GVCH/PYRS
*I
2519319
06/20/08
GVCH/PYRS
Document #: 001-07102 Rev. *L
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CY14B104L, CY14B104N
Document Title: CY14B104L/CY14B104N 4 Mbit (512K x 8/256K x 16) nvSRAM Document Number: 001-07102 Rev. *J ECN No. 2600941 Submission Date 11/04/08 Orig. of Change GVCH/PYRS Description of Change Removed 15 ns access speed Updated Logic block diagram Updated footnote 1 Added footnote 2 and 5 Pin definition: Updated WE, HSB and NC pin description Page 4:Updated SRAM READ, SRAM WRITE, Autostore operation description Page 4:Updated Hardware store operation and Hardware RECALL (Power-up) description Footnote 1 referenced for Mode selection Table Page 6:updated Data protection description Maximum Ratings: Added Max. Accumulated storage time Changed ICC2 from 6mA to 10mA Changed ICC4 from 6mA to 5mA Changed ISB from 3mA to 5mA Updated ICC1, ICC3 , ISBand IOZ Test conditions Changed VCAP max value from 82uf to 180uF Updated footnote 10 and 11 Added footnote 12 Added Data retention and Endurance Table Updated Input Rise and Fall time in AC test Conditions Referenced footnote 15 to tOHA parameter Updated All switching waveforms Added Figure 10 (SRAM WRITE CYCLE:BHE and BLE controlled) Changed tDELAY to 20ns, 25ns, 25ns for 15ns, 20ns, 45ns part respectively Changed tSTORE from 15ms to 8ms Added VHDIS, tHHHD and tLZHSB parameters Updated footnote 21 Added footnote 24 Software controlled STORE/RECALL cycle table: Changed tAS to tSA Changed tGHAX to tHA Added tDHSB parameter Changed tHLHX to tPHSB Updated tSS from 70us to 100us Added Truth table for SRAM operations Updated ordering information and part numbering nomenclature Removed Preliminary form header. Changed tDELAY to 1us (min) and 70us (max) for all three access time Page 4: Removed the text relating to write requested after HSB goes LOW are inhibited. Page 5: modified software store description to indicate no further read/writes permitted for tSS duration after sixth read cycle. Added parameter tPURHH to AutoStore power-Up recall table Updated Figures 11, 12 and 13. Added tHLBL parameter Removed tDHSB parameter Updated Figure 14;Hardware store cycle Changed Simtek trademarks to Cypress
*K *L
2612931 2625431
11/26/08 12/19/08
AESA GVCH/DSG
Document #: 001-07102 Rev. *L
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CY14B104L, CY14B104N
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.
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(c) Cypress Semiconductor Corporation, 2006-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-07102 Rev. *L
Revised December 19, 2008
Page 25 of 25
AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document are the trademarks of their respective holders.
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